TSMC reportedly intends to expand its CoWoS capacity from 8,000 wafers per month today to 11,000 wafers per month by the end of the year, and then to around 20,000 by the end of 2024. But it looks like even then Nvidia will use around half of the capacity that TSMC will have, DigiTimes claims, citing sources familiar with the matter. Meanwhile, AMD is also trying to book additional CoWoS capacity for next year.
Megatrends like 5G, artificial intelligence (AI), and high-performance computing (HPC) are driving adoption of highly complex multi-chiplet designs like AMD’s Instinct MI300 or Nvidia’s H100. It is widely considered that Nvidia is the main beneficiary of the thriving demand for AI-bound compute GPUs, and that it controls over 90% of compute GPU shipments for new deployments. As a result, TSMC is struggling to meet demand for its CoWoS advanced packaging solutions.
TSMC currently has the capacity to process roughly 8,000 CoWoS wafers every month. Between them, Nvidia and AMD utilize about 70% to 80% of this capacity, making them the dominant users of this technology. Following them, Broadcom emerges as the third largest user, accounting for about 10% of the available CoWoS wafer processing capacity. The remaining capacity is distributed between 20 other fabless chip designers.
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